1. Field of the Invention
The present invention relates to a multi-mode power amplifier operable in a low power mode having a preset power range, and, in a high power mode having a power range higher than that of the low power mode.
2. Description of the Related Art
Recently, blocks configuring a wireless transceiver have been implemented using a complementary metal oxide semiconductor (CMOS) process technology and have been integrated in a single chip. However, among these blocks of the wireless transceiver, only a power amplifier has been implemented using an indium gallium phosphide (InGaP)/gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process. However, the above-mentioned InGAP/GaAs HBT process incurs manufacturing costs higher than those of the CMOS process, needs to be implemented in a multi-chip structure, and there may be difficulty in coupling a block formed thereby with an adjusting circuit block implemented by the CMOS process in order to improve linearity. Due to the above-mentioned reasons, research into a CMOS based power amplifier has been actively undertaken.
Meanwhile, among configuring a wireless communications terminal, components associated with power amplification consume the greatest amount of power. Therefore, power amplifier power efficiency needs to be increased in order to improve the entire call time. Since the wireless communications terminal has an output power controlled according to a distance to a repeater, with reference to a probability density function according to an output power of the wireless communications terminal, an efficiency improvement in a low output power backed off from the maximum power output by 10 dB or more has a direct influence on an improvement in call time. That is, there is a need to increase power efficiency not only in a high power mode having the maximum power output level, but also in a low power mode having a power level lower than the maximum power output level.
Therefore, the necessity for a multi-mode power amplifier performing different power amplification operations in a low power mode and a high power mode has been increased.
In the multi-mode power amplifier according to the related art, in the case in which different signal transfer paths are formed for each of the power modes, an impedance matching circuit is required for each of the signal transfer paths, such that a circuit area increases and manufacturing costs rise. Particularly, in the CMOS process, power loss is generated by a passive device for implementing the impedance matching circuit, such that power efficiency is reduced. In addition, even in a case in which an amplifier circuit is formed for each of the power modes, input and output impedance matching circuits are required, such that a circuit area increases and manufacturing costs rise. In addition, power loss may be generated by a passive device, such that power efficiency is reduced.